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Life sciences · Preprint
arXiv · September 3, 2026
Posted before peer review. The findings may change or fail to hold.
LevelSyn is a novel graph neural network-based framework for physical-aware logic synthesis that reports substantial improvements on power and timing over stated baseline methods when evaluated on the EPFL benchmark suite. This is unrefereed algorithmic work without independent validation or peer review; the reported metrics and generalizability to industrial designs remain to be confirmed.
Algorithm validation study on benchmark suite. Industrial-scale integrated circuit designs from EPFL benchmark suite. Intervention: LevelSyn: physical-aware logic synthesis framework with level-asynchronous GNN for gate coordinate prediction and wirelength-driven optimization. Compared with: State-of-the-art (SOTA) methods in logic synthesis and placement prediction (specific baselines not named in abstract).
Average power reduction of 6.89% compared to state-of-the-art methods Timing delay improvement of 27.48% versus SOTA methods Post-place-and-route validation shows 99.59% reduction in design rule check (DRC) violations
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This is an unrefereed arXiv preprint describing a novel computational method for circuit design optimization with reported benchmark improvements; it has not undergone peer review.
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As integrated circuit technology scales into the nanometer regime, the traditional disconnect between logic synthesis and physical design has led to significant PPA (Power, Performance, and Area) degradation and prolonged design closure cycles. Traditional logic synthesis relies on non-physical Wire Load Models (WLMs), while recent spectral-based placement predictors often neglect the inherent hierarchical logic depth and signal flow of netlists, which leads to low-fidelity spatial estimations. To bridge this gap, we propose LevelSyn, a novel physical-aware logic synthesis framework that integrates hierarchical representation learning with a wirelength-driven optimization engine. At its core, LevelSyn leverages a level-asynchronous Graph Neural Network (GNN) to predict high-fidelity gate coordinates by capturing the structural and directional semantics of And-Inverter Graphs (AIGs). To handle industrial-scale designs, a level-aligned subgraph partitioning strategy is introduced to eliminate memory bottlenecks while preserving local logical dependencies. These spatial insights are seamlessly integrated into a newly developed physical-informed synthesis engine within the Berkeley ABC framework. Experimental results on the EPFL benchmark suite demonstrate that LevelSyn significantly outperforms state-of-the-art (SOTA) methods, achieving an average power reduction of 6.89\% and a timing delay improvement of 27.48\%. Furthermore, post-place-and-route validation shows a 99.59\% reduction in design rule check (DRC) violations, highlighting its effectiveness in accelerating design convergence.
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